The present invention relates to a semiconductor device having an advantage of high integrity, and more particularly to an isolation region structure of such a semiconductor device and a method for fabricating the same using both a buried oxide isolation technique and a local oxidation of silicon technique.
Local oxidation of silicon (LOCOS) techniques have been used for isolating adjacent active regions from each other in LSI and VLSI integration of MOS transistors. In accordance with such LOCOS techniques, a thin pad oxide film is interposed between a silicon substrate and a nitride film as an oxidation mask so as to relieve a stress generated due to the thermal characteristic difference between the silicon substrate and the nitride film.
However, such LOCOS techniques involve not only a vertical growth of a field oxide film in field oxidation, but also a lateral diffusion of an oxidant through the stress-relief pad oxide film. As a result, the field oxide film is laterally grown beneath an edge of the nitride film as the oxidation mask.
Due to such a lateral growth, the field oxide film encroaches on an active region, resulting in a decrease of the active region.
Such a phenomenon that the field oxide film encroaches on the active region is called a bird's beak. Such a bird's beak has a length coming up to 1/2 of the thickness of the field oxide film.
For reducing the length of the bird's beak causing a damage of the active region, the thickness of the field oxide film should be reduced. However, such a reduction in the thickness of the field oxide film results in an increase in capacitance between the substrate and each of interconnection lines on a chip. As a result, an IC characteristic is degraded.
Furthermore, the threshold voltage V.sub.T of a parasitic field transistor is decreased, resulting in an increase in leakage current at a region beneath the field oxide film. As a result, an insulating characteristic between adjacent active regions is degraded.
In actual, the method for decreasing the length of bird's beak by decreasing the thickness of the field oxide film is improper as a practical insulating method.
As a result, researches have been made for inhibiting the growth of bird's beak and thus reducing the length of bird's beak without decreasing the thickness of the field oxide film.
One of the methods for inhibiting the growth of bird's beak without decreasing the thickness of the field oxide film is a field oxidation method wherein a pad oxide film is sealed by a nitride film as an oxidation mask formed over the pad oxide film and a nitride film formed in the form of side walls on the side surfaces of the pad oxide film.
As the next generation isolation techniques, there have been known a polysilicon buffered LOCOS isolation using a polysilicon as a stress-buffered layer, a side wall masked isolation (SWAMI) and a sealed-interface LOCOS (SILO) isolation. In addition, the buried oxide (BOX) isolation has been known.
Isolation techniques applicable to devices requiring a high integrity should satisfy the following requirements.
First, an isolation region should have a planar surface. This is for the purpose of solving a problem related to an aspect ratio due to a reduction in lateral dimension of a device finally produced and thereby obtaining a superior pattern limitation characteristic.
Second, a crystal defect should not occur in a bulk of a field region adjacent to an edge portion of an active region;
Third, a zero bird's beak should be produced so as to obtain maximized active regions.
The BOX isolation technique is the isolation technique capable of satisfying the above-mentioned requirements.
Generally, the BOX isolation technique includes the steps of growing a stress-relief oxide film on a silicon substrate, depositing a nitride film over the oxide film, patterning the nitride film and the oxide film to define an active region and a field region, etching a portion of the silicon substrate corresponding to the field region by use of a photolithograpy to form a trench, filling the trench with a CVD oxide film, coating a photoresist film over the resulting structure, and etching back the photoresist film and the CVD oxide film to planarize the surface of the oxide film.
The reason why the photoresist film is coated and then etched back is to planarize the surface of the CVD oxide film filling the trench.
In other words, when the CVD oxide film is deposited to fill the trench, it gets depressed at its portion positioned over the trench having a large width, thereby causing its surface to be uneven. The surface of the CVD oxide film is planarized by use of the photoresist film.
Although the BOX isolation method has advantages of a bird's beak of zero and a planar surface of an isolation region, it encounters the following problems.
First, it involves complex process steps because a photolithograpy process step is carried out twice for achieving the step of forming the trench and the step of planarizing the CVD oxide film.
Second, the surface-planarizing photoresist film may be coated to a non-uniform thickness, depending on a pattern density. As a result, the photoresist film has a smaller thickness at a highly dense region. This requires a critical resist etchback process step. In other words, since the CVD oxide film and the photoresist film are non-uniform in thickness, the surface of the CVD oxide film can not be completely planarized. Upon the etching, the surface of the active region may be considerably damaged.
As an isolation technique capable of obtaining a planar surface without encroaching on the active region and by use of a single photolithography process step, there has been proposed an isolation method wherein adjacent active regions are isolated from each other by use of the LOCOS isolation technique where a large space is defined between adjacent active regions and by use of the BOX isolation technique where a small space (a narrow trench) is defined between adjacent active regions. This method using the LOCOS isolation technique and the BOX isolation technique together has been disclosed in U.S. Pat. No. 4,892,614.
FIGS. 1A to 1H are sectional views respectively illustrating a conventional method for fabricating isolation regions of a semiconductor device by use of both the LOCOS isolation technique and the BOX isolation technique.
In accordance with this method, a thermal oxide film 12 is grown over a silicon substrate 10, as shown in FIG. 1A. A nitride film 14 is then deposited over the thermal oxide film 12 by use of a low pressure chemical vapor deposition (LPCVD) process. A photoresist film 16 is coated over the nitride film 14 and then patterned to define active regions 18. Using the patterned photoresist film 16 as a mask, the nitride film 14 and the oxide film 12 are etched and the silicon substrate 10 is etched so as to form a trench structure including a plurality of trenches 20a to 20d. Each of trenches 20a and 20b has a relatively small width, thereby defining a narrow isolation space between adjacent active regions 18. On the other hand, each of trenches 20c and 20d has a relatively small width, thereby defining a wide isolation space between adjacent active regions 18. In FIG. 1A, the reference numeral 21 denotes corners of each trench.
Thereafter, the photoresist film 16 remaining over the active regions 18 is completely removed, as shown in FIG. 1B. A second thermal oxide film 22 is then grown again over portions of the silicon substrate 10 exposed due to the formation of the trench structure. This thermal oxide film 22 serves to form each corner 21 of each trench into a slightly round shape, as compared with the structure of FIG. 1A.
Over the entire exposed surface of the resulting structure, a second nitride film 24 is deposited, as shown in FIG. 1C. An oxide film 26 having a large thickness is deposited over the second nitride film 24 by use of the CVD process. The oxide film 26 is thickly deposited such that it fills the narrow trenches 20a and 20b sufficiently, but fills the wide trenches 20c and 20d insufficiently. As a result, small depressions 27a are formed at the surface portion of the oxide film 26 over the narrow trenches 20a and 20b, respectively. On the other hand, deep depressions 27b are formed at the surface portion of the oxide film 26 over the wide trenches 20c and 20d, respectively.
Subsequently, an anisotropic etching step is carried out for forming side walls of each trenches, as shown in FIG. 1D. At the anisotropic etching step, respective portions of the CVD-oxide film 26, the nitride film 24 and the thermal oxide film 22 disposed beneath the deep depressions 27b at the wide trenches 20c and 20d are etched. As a result, the silicon substrate 10 is exposed at its portions respectively disposed in the trenches 20c and 20d. Also, each of the trenches 20c and 20d has side wall oxide films 28. Of course, each of the narrow trenches 20a and 20b also has side wall oxide films 28. In this case, however, the side wall oxide films 20 are formed to fill the trench completely. As a result, the nitride film 24 is not etched.
Then, a field oxidation step is carried out for forming a field oxide film, as shown in FIG. 1E. At the field oxidation step, all the side wall oxide films 28 of the trench structure are removed. Formation of a field oxide film 30 is achieved by use of the LOCOS process. At this time, the field oxide film 30 is not grown in the narrow trenches 20a and 20b because the silicon substrate 10 is covered with the nitride film 24 in the narrow trenches 20a and 20b. However, the field oxide film 30 is grown over the silicon substrate 10 in the wide trenches 20c and 20d. In the wide trenches 20c and 20d, the field oxide film 30 is further grown over the edge portions of the nitride film 24, thereby forming bird's beaks 31. In spite of such bird's beaks 31, however, the active regions 18 are not reduced in dimension. This is because the bird's beaks 31 are not grown up to areas over active regions 18.
Thereafter, the nitride films 14 and 24 are dipped in a hot phosphoric acid solution so as to be completely removed, as shown in FIG. 1F. A CVD oxide film 32 is thickly coated over the entire exposed surface of the resulting structure to fill all the trenches and have a planar surface.
The CVD oxide film 32 is then etched back to provide a planar surface, as shown in FIG. 1G.
Over the entire exposed surface of the resulting structure, a third thermal oxide film 34 as a gate oxide film is then formed to obtain isolation regions for isolating active regions 18, as shown in FIG. 1H. The isolation regions have the BOX structure constituted by the CVD oxide film 32 formed in each of the narrow trenches 20a and 20b and the LOCOS structure constituted by the field oxide film 30 formed in the wide trenches 20c and 20d and the CVD oxide film 32 covering over the edge portions of the field oxide film 30.
In other words, the isolation between the active regions 18 at each of the narrow trenches 20a and 20b is achieved in accordance with the BOX isolation technique. At each of the wide trenches 20c and 20d, the isolation between the active regions 18 is achieved in accordance with a combination of the BOX isolation technique and the LOCOS isolation technique.
Accordingly, it can be understood that the method for fabricating isolation regions of a semiconductor device by utilizing both the LOCOS isolation technique and the BOX isolation technique is the isolation technique capable of satisfying the requirements involved in high integration of the semiconductor device, namely, a planar surface, a zero bird's beak, and a simple planarization using a single photolithography process step for trench formation.
In accordance with the above-mentioned method, however, when the CVD oxide film 32 fills the trenches 20 formed in the silicon substrate 10, the filling of CVD oxide film 32 may be incompletely achieved in cases of narrow and deep trenches, thereby forming voids. For preventing such a formation of voids, it is necessary to carry out the deposition of the CVD oxide film 32 at a high temperature of 750.degree. to 800.degree. C. However, such a heat cycle involves a problem of a crystal defect occurring at lower edge portions 21 of the trench structure.
Since the CVD oxide film 32 fills the trench structure, a stress may be applied to the silicon substrate 10 due to a thermal reaction difference (thermal expansion coefficient difference) between the silicon substrate 10 and the CVD oxide film 32 at the heat cycle process step following the formation of isolation regions. As a result, a crystal defect may occur.
Furthermore, the CVD oxide film 32 filling the trench structure exhibits a high etch rate in an HF solution. As a result, the CVD oxide film 32 may be greatly damaged when it is subjected to a cleaning at subsequent process steps following the formation of isolation regions.